The present invention relates generally to test methods used in integrated circuit manufacturing. More particularly, the present invention relates to test methods for determining a value of barrier permeability associated with a test barrier at a via bottom based on a measured lifetime of a test structure containing the test barrier.
As interconnect dimensions scale to smaller sizes and current densities increase in today""s integrated circuits, the reliability of interconnects becomes a greater concern due to increased electromigration rates. Electromigration (EM), which is the diffusion of atoms in an interconnect induced by an electric current, can lead to interconnect failure by voiding or extrusion at sites of atomic flux divergence, that is, where the net flux of atoms is not zero. The net displacement of atoms during EM causes local stress changes in the interconnect in which either tensile or compressive stresses develop as atoms are depleted or accumulated, respectively. Tensile and compressive stresses can develop, for example, at the electron-source (cathode) and the electron-sink (anode) vias, respectively, when the vias are no-flux boundaries, such as W- or Ti-filled vias. Failure of the interconnect will occur, for example, once the stress somewhere in the line exceeds a critical stress required for void nucleation.
One of the purposes of a barrier layer is to prevent mass flow (diffusion of atoms) between the metal layers and the resultant interconnect failures due to electromigration. As device sizes continue to shrink, barrier materials must become thinner in order to minimize resistance at the vias. However, the thinning of the barrier may cause the interface of the via/feeder-line to become permeable to mass flux and lead to EM failures.
FIG. 1A illustrates a cross-sectional view of a two metal layer interconnect structure 100 having a first conductor 105, a second conductor 110, a third conductor 115, respectively. A barrier layer 120 is disposed between the first conductor 105 and the second conductor 110 at a cathode via 125 and disposed between the second conductor 110 and the third conductor 115 at an anode via 130. The second conductor 110, having a length L 135, forms an interconnect between the first and third conductors. Length L 135, is measured from the via at one end of the interconnect line to the via at the other end. FIG. 1A also illustrates the tensile stresses 140 which can develop in the region of the cathode via 125, and the compressive forces 145 which can develop in the region of the anode via 130 as electrons flow from the cathode to the anode. Typically, the layers may be formed, for example, using conductors of Al, Al alloy, with a TiN barrier layer, or using Cu conductors, with a TaN barrier layer.
FIG. 1B shows a cross-sectional view of another two metal layer interconnect structure 150 similar to the structure 100 illustrated in FIG. 1A. FIG. 1B illustrates a common failure mode due to voids 160 which typically form in areas of the highest tensile stresses (e.g., 140 of FIG. 1A), near the region of the cathode via 125. Mass flux-divergence taking place at the electron-source (cathode) vias, produces maximum tensile stresses in this region. When these tensile forces reach a critical stress level, void nucleation occurs. Eventually, if a high enough current density is maintained through the interconnect, failure of the interconnect may result due to electromigration (EM failure).
FIGS. 1A and 1B also illustrate the conventional EM test structures which attempt to determine the lifetime of such structures, to analyze the effects of EM on various structures, or the effect of a barrier layer on EM. In the conventional method, current is conducted from the cathode conductor to the anode conductor until the resistance of the test structure reaches a predetermined failure criterion. Conventional methods measure the lifetime of the test structure, or may even indicate improved or worsened lifetimes, but do not quantify a specific barrier parameter associated with the structure""s lifetime.
In addition, conventional two-level EM test structures often have feeder lines that are much wider than the test line and therefore are insensitive to the permeability of the barrier at the via since mass flow from the feeder line to the via is negligible when compared to the volume of the feeder line.
Currently, some conventional EM test structures rely on an assumption that a barrier layer being tested has no mass flux entering from the cathode/feeder line, but may in fact, have a mass flux which may reduce or invalidate the effectiveness of testing lifetime measurements associated with specific parameters of the barrier which are under investigation.
Accordingly, there is a need for quantifying a specific barrier layer parameter associated with the lifetime of a test structure during electromigration in a test structure.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a method of determining a barrier permeability, wherein a barrier permeability value is assigned to a test barrier based on a measured lifetime of a test structure used in integrated circuit manufacturing.
In the present invention a new EM test structure is also proposed in order to not only detect the permeability of a barrier/via, but also to allow for the quantifying of the degree of permeability, herein symbolized as (xcex1). According to one aspect of the invention, this may be accomplished using experimental lifetimes from different barrier permeability structures and by EM simulation.
The new EM test structure allows for the assessment of barrier permeability xcex1 at the via/supply-line barrier interface. The new test structure also assures the prevention of mass flux through the barrier from, for example, the cathode via of the test line, by providing a no-flux barrier (flux blocking boundary) at the cathode end of the test line. This no-flux barrier guarantees that a void will not form beyond the test line, via, or supply line. Such a boundary may be formed, for example, by depositing a much thicker barrier in the test line, while depositing the barrier of interest in the supply line.
The present invention provides a method for determining the magnitude (e.g., degree, extent) of permeability of a barrier at a via. A test structure is formed having a test barrier between two conductors. A substantially constant current is conducted through the test structure while measuring the time to failure (lifetime) of the test structure. A barrier permeability value is assigned to the test barrier of the test structure based on the measured lifetime.
In an aspect of the present invention, a processor or computer simulator, for example, may be provided to supply simulation lifetime data which is generally associated with the test structure. The simulator; for example, matches a measured lifetime tREAL to a simulation lifetime tSIM. The method then assigns a barrier permeability value to the test barrier from a simulation lifetime permeability xcex1SIM corresponding to the simulation lifetime tSIM which is based on the measured lifetime tREAL. The measured lifetime tREAL may be any value of time, based on the actual measured time until a failure of the test structure is determined.
Another aspect of the present invention further provides a method wherein, a second test structure is provided. The second test structure comprises a first conductor, a second conductor, wherein the second conductor forms an interconnect, and a third conductor, respectively. A first no-flux barrier is disposed between the first and second conductor, and a second no-flux barrier is disposed between the second and third conductor, wherein the first and second no-flux barrier are substantially impermeable to mass flux, and are substantially identical to the no-flux barrier of the first test structure. The exemplary method conducts a current through the second test structure, while measuring a lifetime of the second test structure, to confirm whether the no-flux barrier of the first test structure is substantially impermeable to mass flux based on the lifetime of the second test structure.
For example, the second test structure may have a much thicker barrier disposed between the first and third conductors, or a different material and thickness by which mass flux is prevented from traveling from the cathode end. The first and second no-flux barriers of the second test structure are intended to be substantially identical to the no-flux barrier of the first test structure, to test verify that the no-flux barrier of the first test structure is truly impermeable to mass flux.
In another example of the present invention, the system includes a test structure having a first conductor, a second conductor forming an interconnect, and a no-flux barrier substantially impermeable to mass flux between the first and second conductor. The structure further comprises a third conductor and a test barrier disposed between the second and third conductor, to be assessed for the barrier permeability value. A constant current source, for example, supplies the current through the test structure. A timer measures the lifetime of the test structure, and a processor determines the value of barrier permeability xcex1 of the test barrier based on the measured lifetime of the test structure.
Yet another exemplary aspect of the present invention provides a system, wherein the timer further comprises a detector to measure a change of resistance of the test structure, wherein a time to failure of the test structure is measured while measuring a change of resistance of the test structure. For example, the time at which the resistance of the test fixture changes from an initial resistance by some predetermined percentage may be used to determine that the test structure has failed, thereby defining the lifetime of the test structure.
The aspects of the invention find application in devices which include semiconductors, integrated circuits, and the manufacturing of such devices.